LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY load_unit IS
PORT
	(
		clk		           : IN STD_LOGIC;
		
		data_ram_input  : in std_logic_vector(35 downto 0);
		data_ram_addr   : in unsigned(6 downto 0);
		data_ram_wren   : in std_logic;
		
		request_addr    : in unsigned(6 downto 0);
		request_enable  : in std_logic;
		
		data_ram_output : out unsigned(31 downto 0);
		data_ram_valid  : out std_logic
		
	);
END load_unit;



ARCHITECTURE bhv OF load_unit IS

   signal	rdaddress		:  unsigned (6 DOWNTO 0) := (others => '1');
   signal q  : std_logic_vector(35 downto 0);
   signal request_enable_buffer : std_logic := '0';
   
    
   component data_ram IS
	 PORT
	 (
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (35 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
	 );
   END component;
  

BEGIN
  
  
  data_ram1 : data_ram
	PORT map
	(
		clock		=> clk,
		data		=> data_ram_input,
		rdaddress		=> std_logic_vector(request_addr),
		wraddress		=> std_logic_vector(data_ram_addr),
		wren		=> data_ram_wren,
		q		=> q
	);
	
	
	process (clk)
	begin
	 if rising_edge(clk) then
	     rdaddress <= request_addr;
	     
	     if request_enable='1' then 
	       request_enable_buffer <= '1';
	     end if;
	     if request_enable_buffer='1' and rdaddress = request_addr then
	       request_enable_buffer <= '0';
	     end if;
	       
	 end if;
	end process;
	
	
	data_ram_output <= 	unsigned(q(31 downto 0)) ;
	
	data_ram_valid <= '1' when request_enable_buffer='1' and rdaddress = request_addr else '0';

END bhv;


